1. Field of the Invention
The present invention relates to a memory system which is formed by combining a flash EEPROM type nonvolatile memory for file storage, such as a NAND flash memory, having a large capacity but requiring a long read shift time, long programming time, and long erase time, an FeRAM having a medium capacity but capable of high-speed read/write, and a controller which controls the nonvolatile memory and FeRAM. This memory system makes it possible to increase the speed of read/write of data having a small file size, increase the speed of read/write of, e.g., a file allocation table (FAT) and directory information, prevent deterioration of the performance of reading/writing effective data caused by, e.g., allocation table write necessary as a measure to cope with an instantaneous power failure, increase the speed of data to be frequently read or written, and facilitate changing the specification of the controller.
2. Description of the Related Art
Semiconductor memories are presently widely used in many apparatuses such as main memories of mainframe and personal computers, household electric appliances, and cellphones. Those which are predominate in the market are flash EEPROM type nonvolatile memories represented by a NAND flash memory, and various types of memory cards (SD card, MMC card, MS card, and CF card) are used as media for storing information such as still images, motion images, sounds, and games in storage media of, e.g., digital cameras, digital videos, music players such as MP3, mobile PC's, and digital TV. USB compatible cards are also extensively used as storage media of PCs.
The flash EEPROM type nonvolatile memories are roughly classified into a NOR memory and NAND memory. The NOR memory can perform high-speed write, and can also perform read about 1013 times. This NOR memory is used to store instruction codes in a mobile gear. However, the NOR memory is unsuitable for file recording because the effective bandwidth of write is small.
On the other hand, the NAND memory can be highly integrated compared to the NOR memory. Although the access time is as long as 25 μs, burst read can be performed, and the effective bandwidth is large. Also, the program time and erase time of write are as long as 200 μs and about 1 ms, respectively, but a large number of bits can be programmed or erased at once. This makes it possible to load write data in a burst manner and program a large number of bits at once. Therefore, the NAND memory is a memory having a large effective bandwidth. By making the most of these advantages, the NAND memories are used in memory cards and USB memories as described above, and are recently used in memories of cellphones.
FIGS. 1A to 1C each show the memory cell structure of a NAND flash EEPROM, in which FIG. 1A shows a planar layout of a cell block, FIG. 1B shows a sectional view of a memory cell, and FIG. 1C shows an equivalent circuit of the cell block. As shown in FIG. 1C, a plurality of floating gate type transistors are arranged in series, and selection transistors are arranged between one terminal of the series circuit and a bit line BL and between the other terminal of the series circuit and a source line SL. Since memory cells are arranged one by one at the intersections of word lines WL0, WL1, . . . , WL7 and the bit line BL, this memory is most suitable for high integration.
FIG. 2 shows the arrangement of a memory cell array in which the cell blocks described above are arranged. A unit for performing erase is a memory cell block unit shown in FIGS. 1A to 1C when viewed in the bit direction, and is one entire mat when viewed in the word line direction. This erase unit has a capacity of about 256 KB. The erase unit is divided into a plurality of units, and each divided unit is called a block. A program unit corresponds to one word line in the erase block and every other bit line (an even-numbered bit line EvenBL or odd-numbered bit line OddBL). When the number of series-connected cells is 32, the program unit is 256 KB/32/2=4 KB. This program unit is called a page. In this example, the block/page ratio is 64. One of the odd-numbered bit lines OddBL and even-numbered bit lines EvenBL is read in a read operation as well. When the even-numbered bit line EvenBL is to be read, for example, the odd-numbered bit line OddBL is set at Vss in order to reduce the interference noise between them.
FIGS. 3A to 3D illustrate examples of read, program, non program, and erase operations of the NAND flash, respectively. In the read operation, the word line of a cell to be read are set at 0V, and the rest is changed to High. If a threshold voltage Vt of the cell transistor is Vt<0, the potential of the bit line BL lowers. If Vt>0, the bit line BL stays High, and the cell data is read out.
In the erase operation, the well potential of the whole cell block is set at 20V, and the rest are set at 0V, thereby drawing electrons of the floating gate to the well by a tunneling current to make the threshold voltage Vt lower than 0V. Accordingly, the erase unit is a large unit of 256 KB.
The program operation is performed by respectively setting the word line and bit line of a selected cell at 20V and 0V, thereby raising the threshold voltage by injecting electrons into the floating gate by a tunneling current.
In this state, the word line of each unselected cell in the same block is set at about 7V to decrease the applied voltage to an unselected transistor and suppress write. For a bit not to be written of the selected word line, the bit line is set at 7V, and an unselected word line is raised to 7V to boot the source and drain voltages of the cell transistor, thereby suppressing write. This example is a binary method which stores 1-bit information in one cell. Recently, however, a quaternary method which stores 2-bit information in one cell is beginning to be used.
FIG. 4 is a schematic diagram showing a case in which four values are given to the threshold voltage of one cell (cell transistor). In the first programming, 1 or 0 is written in a lower bit. In the second programming, an upper bit is written. This gives the four threshold voltage distributions of the cell. Although this quaternary method is suited to increasing the density, the threshold voltage Vt of the cell transistor must be suppressed to the distribution within a narrow range. This makes the program time and erase time longer than those of the binary method. In addition, a read operation requires determination at least twice, so it takes a long time to start reading out data.
As other flash EEPROMs, memories called AND and DINOR are known. The AND memory is suitable for high speed write and used as a file storage memory. The DINOR memory is similar to the AND memory, but suitable for high speed read and mainly used as an instruction code storage of a cellphone or the like.
In a memory system such as a memory card using the NAND flash described above or the like, one or several NAND flashes and a controller for controlling the NAND flash or NAND flashes are mounted on the card. This controller has the four functions described below.
First, the controller has an interface circuit on the host side, and performs read/write from the host to the NAND.
Second, the controller has an interface circuit of the NAND, and performs read/write from the NAND to the host.
Third, the controller performs address management/bad block management and the like when writing data in the NAND.
Fourth, the controller controls write to a block corresponding to, e.g., a FAT or directory by using a relatively small unit smaller than the block.
In the memory system using the NAND flash described above, however, data holding basically takes a long time for read/program/erase, and this time further prolongs on the card level or OS level. In particular, read/write of a small file is the worst case.
One solution to this problem is to use a ferroelectric memory (to be referred to as an FeRAM hereinafter) as a nonvolatile memory capable of high-speed read/write as a storage medium similarly to a DRAM, and also capable of storing information even when the power supply is turned off. In addition to the ability to perform high-speed read/write, the ferroelectric memory can be rewritten 1013 to 1016 times, has a read/write time equivalent to that of a DRAM, and can operate at 3 to 5V. The ferroelectric memory having these advantages is also called an ultimate memory. The use of the ferroelectric memory can solve the problem of slow read/write of the NAND flash.
Unfortunately, the FeRAM is presently not so highly integrated as the NAND flash, and therefore incurs a high cost.
The FeRAM will be briefly explained below. FIG. 5A shows a memory cell having one transistor and one capacitor of a conventional ferroelectric memory. In this memory cell of the conventional ferroelectric memory, the transistor and capacitor are connected in series. A memory cell array includes a bit line BL for reading out data, word lines WL0 and WL1 for selecting a transistor, and plate lines PL0 and PL1 for driving one terminal of the ferroelectric capacitor.
In this conventional ferroelectric memory, however, to prevent destruction of polarization information in the ferroelectric capacitor of an unselected cell, the plate lines are disconnected by the word lines and must be individually driven. Accordingly, a driving circuit of the plate lines is as very large as 20% to 30% of the chip size, and the plate line driving time is long.
To solve the above problem, the present inventors have proposed a new nonvolatile ferroelectric memory capable of simultaneously achieving (1) a small memory cell, (2) a readily fabricable planar transistor, and (3) a versatile high-speed random access function in prior applications (Jpn. Pat. Appln. KOKAI Publication Nos. H10-255483, H11-177036, and 2000-22010). FIG. 5B shows the arrangement of this ferroelectric memory of the above prior applications. In the prior applications, one memory cell is formed by connecting a cell transistor and ferroelectric capacitor in parallel and one memory cell block is formed by connecting a plurality of parallel circuits of memory cells in series. One terminal of the block is connected to a bit line BL via a block select transistor, and the other terminal of the block is connected to a plate line PL. The operation is as follows. In a standby state, as shown in FIG. 6A, all word lines WL0, WL1, . . . , WL3 are changed to High to turn on the memory cell transistors, and a block select signal BS is changed to Low to turn off the block select transistor. Since the two terminals of the ferroelectric capacitor are electrically shorted by the ON transistor, no potential difference is produced between them, so the stored polarization is stably held.
In an active state, as shown in FIG. 6B, only a transistor connected in parallel to a ferroelectric capacitor to be read is turned off, and the block select transistor is turned on. After that, the plate line PL and block select signal BS are changed to High. Accordingly, the potential difference between the plate line PL and bit line BL is applied only to the two terminals of a ferroelectric capacitor C1 connected in parallel to the off-transistor, so polarization information of this ferroelectric capacitor is read out to the bit line BL. Although the cells are connected in series, therefore, cell information of a given ferroelectric capacitor is read out by selecting a given word line, so complete random access can be realized. Also, since the plate line can be shared by a plurality of memory cells, it is possible to increase the area of a plate line driving circuit (PL driver) while the chip size is reduced, and to realize a high-speed operation.
In addition, the present inventors have proposed a ferroelectric memory capable of an ultra high speed operation in Jpn. Pat. Appln. KOKAI Publication No. 2005 209324. In this memory, as shown in FIG. 5C, a ferroelectric capacitor and cell transistor are connected in series to form each cell, and a plurality of cells are connected in parallel. A reset transistor is further connected in parallel to this parallel circuit, and the obtained paralled circuit is connected to a bit lie via a block transistor. This ferroelectric memory can achieve the effects of the prior applications described above, and can also further increase the operating speed by the effect of connecting the series circuits of cells in parallel. This is so because in the standby state, it is possible to short circuit all ferroelectric caps via the reset transistor by turning on all the cell transistors, and to share the plate driving line, unlike in the conventional ferroelectric memory.
When this ferroelectric memory is in the standby state, as shown in FIG. 6C, all word lines WL0 to WL3 are changed to High to turn on the transistors, a reset signal RST is changed to High to turn on the reset transistor, and a block select signal BS is changed to Low to turn off the block select transistor. In this manner, the two terminals of the ferroelectric capacitor is set at the potential (0V) of a plate line PL.
In the active state, as shown in FIG. 6D, only a transistor connected in series with a ferroelectric capacitor to be read is turned on, the reset transistor is turned off, and the block select transistor is turned on. After that, the plate line PL is raised from 0 to 1.9V, thereby applying the potential difference between the plate line PL and bit line BL only to the two terminals of the ferroelectric capacitor C2. Consequently, polarization information of the ferroelectric capacitor C2 is read out to the bit line BL.
As shown in FIGS. 7A and 7B, an MRAM is also proposed as a nonvolatile memory capable of high-speed read/write. This MRAM is a memory in which a thin film of, e.g., Al2O3 is sandwiched between magnetic layers (fixing layer and free layer), and an electric current in the thin film increases if the spin directions in the upper and lower magnetic layers are the same, and reduces if the spin directions are opposite. This difference gives the memory a binary value.
Although the MRAM is capable of high-speed read/write similarly to the FeRAM, the chip size is larger and the cost is higher than those of the NAND flash. A phase change memory (also called a PRAM) having a relatively short write time is also proposed, but the cost of this memory is also high.
As described above, a memory system using the flash EEPROM or the like is slow in read and takes a long program/erase time. In addition, extra system information must be written on the card level or OS level, and this further extends the time. In particular, read/write of a small file is the worst case.
One solution to this problem is a memory system using a nonvolatile memory such as an FeRAM, MRAM, or PRAM capable of high-speed read/write. However, a nonvolatile memory of this type poses another problem of high cost.